GCC optimizations and 68000 cycle counter
[ Atariscne.org - News ] GCC optimizations and 68000 cycle counter
PeyloW of T.O.Y.S. have been busy lately by optimizing the GNU C Compiler (GCC) v15.2 to create faster code for 68000 processor.
The improvements include using proper dbra/dbf loops, auto inc/dec of address registers (you know, the stuff that is nice on 68k!).
PeyloW writes in an Atari-Forum post:
At a very high level there are 7 groups of changes made:
- Cost Model - More accurate cost models, allowing gcc to chose better.
- Register Allocation – Adopt LRA, and tune to prefer fewer registers.
- Loop Optimization – Adopt new doloop hooks to enable more explicit use of dbra.
- Memory Access Reordering – More of cleanup pass for other optimisations, try to ensure memory access is sequential.
- Autoincrement Optimization – Which allows more auto increment to be used instead of indexed addressing.
- 16/32-bit Optimization – And merging of 2x word accesses into single long access. Also narrow mulu/muls operators to word size if operand sizes can be determined at compile time.
- Various Smaller Optimizations – Grab bag of stuff. Single bit extraction bit btst/tas, and simple peephole optimizations.
While working on GCC, PeyloW also developed a separate tool to count 68000 cycles out of assembler sourcecode to easily check if the compiler changes actually improve stuff - but can certainly can be very useful for other purposes as well.
Both projects can be found on Github, see links below.
🔗 m68k GCC Build Scripts and Documentation